| 摘要 |
PURPOSE:To generate a synchronizing signal even concerning reception data, for which the number of flags is determined in advance, by detecting the flag in the reception data, generating the synchronizing signal corresponding to the number of flags, and delaying the reception data by the prescribed number of bits. CONSTITUTION:When the reception data are supplied to a shift register 1a of a detection circuit 1 and the reception data are '01111110', a pulse signal with a one-bit length at an H level is sent out. As a result, the output signal of a counter constituting a synchronizing signal generation circuit 2 is reset, and goes to a signal state at an L level synchronously with the rise of the pulse signal 10. Since the number of bits for the flag is '8' and the pulse signal with the one-bit length is generated by the detection circuit 1, a delay circuit 3 delays the reception data by 7 bits. Thus, a data part 11 of the reception data is synchronized to a synchronizing signal 12 at the H level to be sent out from the synchronizing signal generation circuit 2. |
