| 摘要 |
<p>PURPOSE:To shorten time for reading data and for control from an external part and to synthesize the data in the internal parts of memory cells by connecting plural address decoder outputs to word lines and forming a wired OR as a whole. CONSTITUTION:When the data are read out, a precharge signal 'H' is inputted to a line 7 and supplied through an inverter 14 to a precharge circuit 5. An address signal is inputted through a line 8 to each address decoder 2. The respective word lines and respective address decode output buffers 11 connected to those lines form the wired OR. Only an N-Tr in memory cells 1-1 and 1-2 is turned ON and the respective memory data are outputted to bit lines 4-1 - 4-4. Then, on the bit lines, the respective memory data are synthesized and outputted through a bit output buffer.</p> |
