HIGH-SPEED DYNAMIC CMOS CIRCUIT

摘要

Programmable logic array, multiplexer and memory array circuits utilizing the dynamic CMOS logic of the invention are capable of operating at speeds approximating twice that of similar circuits utilizing conventional dynamic CMOS logic. The circuit of the invention has an AND plane defined by a series of input columns (64) and a series of rows (68), and has an OR plane defined by the series of rows (68) and one or more output columns (69). Transistors (70, 71) are connected selectively between the input columns (64) and the rows (68), and between the output columns (62) and the rows (68). During one state of an external clock input (Ø1) to the circuit each of a series of inputs (A, B, C) are placed on a respective one of the input columns (64), each of the output columns (69) are precharged, and each of the rows (68) is discharged. The shifting of the external clock (Ø1) input to the alternate state results in latching of the values on the input columns (64) and in termination of the output column precharging (69) and row discharging (68). Charge is then injected into each of the rows (68), and propagates through both the AND and OR planes while the external clock input (Ø1) is still in the alternate state. Unlike conventional two-plane dynamic CMOS logic circuits, there is no need for clocking circuitry intermediate of the two planes.