发明名称 FORMATION OF INTEGRATED CIRCUIT
摘要 PURPOSE: To enhance accuracy of matching various levels of an integrated circuit by improving the detection performance using the electron beam of an electron beam lithograph in a step for enhancing the registration features thereby avoiding double mismatch problems. CONSTITUTION: A resist layer is exposed to an electron beam at a selected position according to a desired pattern of polysilicon gate 122. Correct position of electron beam implantation is determined by detecting an emphasized registration mark defied by the end parts 110, 111 of an oxide region layer 11 using an electron beam. End parts 141, 142 of a silicide layer 14 can be detected more easily than the end parts 110, 111 of an oxide region layer 11 when the silicide layer 14 is missed by backscattering of the electron beam. After exposure to the electron beam, the resist layer is grown and the polysilicon layer is etched using the grown resist layer as a protective layer for etching. Consequently, a polysilicon gate electrode 122 having left and right end parts 114, 115 is formed.
申请公布号 JPH0366116(A) 申请公布日期 1991.03.20
申请号 JP19900184435 申请日期 1990.07.13
申请人 AMERICAN TELEPH & TELEGR CO <ATT> 发明人 ROBAATO RUISU KASUTERAKU JIYUNIA;UIRIAMU TOOMASU RINCHI;SHIIRA BAIJIYA
分类号 H01L29/73;H01L21/027;H01L21/30;H01L21/331;H01L21/8249;H01L23/544;H01L27/06;H01L29/732 主分类号 H01L29/73
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