| 摘要 |
PCT No. PCT/JP84/00597 Sec. 371 Date Aug. 14, 1985 Sec. 102(e) Date Aug. 14, 1985 PCT Filed Dec. 14, 1984 PCT Pub. No. WO85/02716 PCT Pub. Date Jun. 20, 1985.A semiconductor integrated circuit comprising semiconductor regions in the form of first and second protruding poles that are provided on a semiconductor layer formed on a semiconductor substrate or an insulating substrate, and that are opposed to each other with an insulating region sandwiched therebetween, a p-channel FET provided in the first semiconductor region, and an n-channel FET provided in the second semiconductor region. These FET's have source and drain regions on the upper and bottom portions of the semiconductor regions, and have gate electrodes on the sides of the semiconductor regions. The insulation region between the protruding pole-like semiconductor regions is further utilized as the gate electrode and the gate insulating film. |
