| 摘要 |
PURPOSE:To enable a pattern generated in simulation for a single user cell to be used as it is in the simulation for whole of a chip by providing a means to select whether the output signal of a frequency division circuit or a signal from an external terminal is supplied to a user cell as a clock. CONSTITUTION:At a case other than the simulation of the user cell, switching circuits 43, 44 are energized and switching circuits 42, 45 are interrupted since a test mode signal is set at 0, therefore, the outputs 50, 51 of the frequency division circuit 34 go to system clocks phi1, phi2. In the simulation of the user cell, the test mode signal is set at 1, and the switching circuits 43, 44 are energized, and the circuits 42, 45 are interrupted, therefore, the signals inputted to terminals 8 and 41 go to the system clocks phi1, phi2, respectively. Thereby, it is possible to use a simulation pattern for the single user cell as it is as the pattern in the simulation for the whole of the chip. |
