发明名称 COUNTER CHECKING CIRCUIT
摘要 PURPOSE:To reduce the hardware quantity and to shorten a parity check time by detecting a fact that the count value of a counter circuit reaches a specific level and deciding whether the parity is correct or not based on the output of a detection means which detected the specific count value and the output of the corresponding parity bit. CONSTITUTION:A specific value detection means 37 detects a fact that the count value of a counter circuit 1 reaches a specific level, e.g. all-zero. A deciding means 39 decides whether the parity is correct or not based on the output of the means 37 and the output of the corresponding parity bit P. For instance, the presence of a parity error is decided when the output of the means 39 is equal to '1'. Then the absence of a parity error is decided with the output '0' of the means 39. As a result, the hardware quantity is reduced and the parity check time is also shortened.
申请公布号 JPH0364213(A) 申请公布日期 1991.03.19
申请号 JP19890200875 申请日期 1989.08.02
申请人 FUJITSU LTD 发明人 HOSHI KENJI;SUDO KIYOSHI;SAKURAI YASUTOMO;ODAWARA KOICHI
分类号 H03K21/40;H03M13/00 主分类号 H03K21/40
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