| 摘要 |
A video subsystem has a CRT (cathode ray tube) display, video controller and video memory for CRT data which requires access by the controller and a CPU (control processing unit). The subsystem monitors activity of the CRT screen display and the video controller and anytime CRT screen display is not required regardless of the time of occurrence, the CPU is allowed to have access to the video memory during the cycle or cycles in which such inactivity of display occurs. A guaranteed minimum number of cycles is assured for access of the video memory by the CPU using a fixed access sequence during the display periods of a high speed mode and shifting to an arbitration strategy to allow CPU access to occur during non-display times of the high speed mode so that the CPU can acquire more cycles to reduce any backlog of requests as necessary. In a low speed mode, the subsystem automatically changes strategy so that arbitration occurs both during display and non-display periods so that the CPU can acquire memory cycles on an as needed basis.
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