FREQUENCY AND PHASE DETECTING CIRCUIT OF NRZ BIT SYNCHRONIZING SYSTEM

摘要

PURPOSE: To reduce jitter components by extracting phase difference between retimed NRZ data and inputted NRZ and extracting phase difference between the data retimed by the same phase and the opposite phase clocks. CONSTITUTION: A VCO clock is separated into the same and opposite clocks by the same phase and the opposite phase generating circuit U1. As the same phase clock is inputted to the clock terminal Cp of DFFU 2 and the opposite phase clock is inputted to the clock terminal P of DFFU 3, NZR data outputted from U2 and U3 is alternately retimed each time of the transition of the VCO clock. Consequently, concerning retimed NGR data outputted from the outputs Q of U2 and U3, the phase is advanced or delayed by 1/2 period of a VCO clock. Then, when the exclusive OR of the outputs Q of U2 and U3 are taken, a time interval pulse with the time interval of 1/2 period of VCO clock is generated form the output terminal of an exclusive OR gate U4b each time of the transition of NZR data.