发明名称 TELEVISION RECEIVER
摘要 PURPOSE:To simplify designated logic and to maintain privacy performance by constituting a paid television receiver with a vertical pulse generating section, a pseudo random number generating section, a video field memory section and a memory line address designation logic obtaining a start line number for each field. CONSTITUTION:A trigger signal 6 is generated from a vertical pulse generating section 7, a shift clock generating section 3 receives the signal to generate a shift clock 5. A pseudo random number bit string 10 is obtained from a feedback shift register section 4 in response to the signal 5 and it is converted in parallel to obtain a parallel pseudo random number string 34. A memory line address designation logic section 11 reads a video signal written in a field memory section 13 from a line different from each field. Thus, the management and operation of the system are simplified without deteriorating privacy performance.
申请公布号 JPH0362790(A) 申请公布日期 1991.03.18
申请号 JP19890198898 申请日期 1989.07.31
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 OGASAWARA KATSUICHI
分类号 H04N7/16;H04N7/167;H04N7/169 主分类号 H04N7/16
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