| 摘要 |
WYNER-ASH error-correcting coder/decoder applicable to all these codes, including shortened codes, coding and decoding being carried out in series. It includes transmission/reception switchover means (12, 108, 32, 20), elastic rhythm acceleration (15) and deceleration (102) memories, a parity generator (23) with JK flip-flops, driven by a binary counter (33), a comparator (79) associated with this counter (33) and with a syndrome shift register (50), a syndrome generator (54), a delay circuit (58), and an error corrector (98). The delay circuit (58) and the shift register are parametrable by the parameters p and k of the code used. <IMAGE>
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