| 摘要 |
PURPOSE:To accomplish a higher failure coverage by combining a weighted pseudo random pattern with a circuit to be inspected which is incorporated inside an LSI through a bus only used for inspection as an inspection pattern generator. CONSTITUTION:The weighted pseudo random pattern generation circuit (WPPG) 2, a test control circuit (TC) 4, a signature circuit (SIG) 5 and the circuit to be inspected(CUT) 3 are integrated on an LSI chip 1, and they are connected to a test bus 6. The (WPPG) 2 generates an inspection pattern, which is inputted in the CUT 3 by the command of the (TC) 4, then a logical signal is propagated in the CUT 3 by the command. Thereafter, the specified signal value of the (CUT) 3 is outputted to the test bus 6 by the (TC) 4, and the (SIG) 5 inputs the signal and performs data compression. The above operation is repeated specified times and the value which is the result of the operation is read out. When the value coincides with an expected value, it is judged that there is no fault in the circuit 3. Thus, the high failure coverage is accomplished. |
