| 摘要 |
PURPOSE:To sharply shorten a test time by means of a minimum adder circuit by providing the cache memory with a means for inhibiting the generation of an external bus cycle for reading out data to be accessed from a main memory device at the time of generating a cache miss in a test mode. CONSTITUTION:When the inverse of TEST signal is in the low level, i.e. when the test mode is set up, the output of an AND gate 63 is fixed on the low level, so that nodes A, B are respectively fixed on the low and high levels independently of the level of a MISS signal and a TWRITE signal is fixed on the low level. Namely, the rewriting of the contents of a tag memory 1 is inhibited by the operation of latch circuits 61, 62 in the test mode. Thereby, the generation of the external bus cycle for inputting external data at the generation of a cache miss in the test mode is inhibited and the test time is shortened by the minimum adder circuit. |
