发明名称 READING CIRCUIT FOR MEMORY
摘要 <p>PURPOSE:To set a comparison current by arranging in parallel a pair of memory elements, one of which that is the same structure as a memory element is in a write state and the other in a deleted state as comparison elements. CONSTITUTION:A pair of the memory cells 4 and 5, one of which having the same structure as the memory element 3 is in the write state and the other is in the deleted state are arranged in parallel and constituted as the comparison elements. The mean of the currents in the write and deleted states of the memory cells can be set as the comparison current Iref. Since the memory cells 3-5 are the same size, it comes to be Iref=IM(writing)+IM(deletion)=2X(IM (writing)+IM(deletion))-/2 and the current twice as much as the mean value comes to flow. Thus, the size of a transistor is changed in such a way that the current value of a p-channel type transistor 2' comes to twice as much as a p-channel type transistor 1. Thus, the comparison current Iref can be set.</p>
申请公布号 JPH0359887(A) 申请公布日期 1991.03.14
申请号 JP19890194795 申请日期 1989.07.27
申请人 NEC CORP 发明人 SATO HIDEKI
分类号 G11C29/00;G11C16/06;G11C17/00;G11C29/04 主分类号 G11C29/00
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