| 摘要 |
PURPOSE:To evade malfunction of the semiconductor integrated circuit even with the effect of inter-wiring capacitance by arranging a dynamic signal line precharged to a logical high level (H level) and a dynamic signal line precharged to a logical low level (L level) alternately. CONSTITUTION:With an L level applied to a clock input terminal 3, dynamic signal lines 16, 18 are precharged to an H level and a dynamic signal line 17 is precharged to an L level. As soon as a clock input terminal 3 goes to an H level, an H level is applied to input terminals 10, 12. When the dynamic signal line 17 is at an L level and an H level is applied to the input terminals 10, 12, the level of the dynamic signal lines 16, 18 changes from an H level to an L level. Since the plural dynamic signal lines are precharged alternately to the logical high and low level in this way, the integrated circuit does not malfunction even with the effect of the inter-wire capacitance 20. |
