| 摘要 |
PURPOSE:To attain stable bit phase synchronization even to an ultrahigh speed signal by outputting a data signal segmented around its pulse width center with a system clock based on the result of phase difference detection as an output data signal. CONSTITUTION:The bit phase synchronizing circuit consists of a data selection output section 20, a signal state change point detection section 21, a data clock phase difference detection section 22, a data selection control section 23 and a data output section 24. Every time a data signal is sequentially selected by the data selection output section 20, the relation of phase between a changing point of time of the state of the signal and leading and trailing point of time of a system clock is discriminated and when the relation is a prescribed relation, it is discriminated to be in the bit phase synchronizing state, the data signal is segmented at the leading or trailing of the system clock while the data signal is being selected. Thus, stable bit phase synchronization is attained even to an ultrahigh speed signal. |
