| 发明名称 |
HIGH EFFICIENCY CODING DEVICE |
| 摘要 |
PURPOSE:To prevent generation of mismatching between the encoder side and the decoder side by applying the buffering processing based on an original dynamic range DR, comparing a corrected dynamic range DR' and a threshold level decided by the buffering processing so as to apply quantization. CONSTITUTION:A bit number decision circuit 19 receives an output signal of a comparator circuit 20. A corrected dynamic range DR' from a subtraction circuit 15 and threshold levels T1-T4 (T1<T2<T3<T4) from a buffering circuit 21 are fed to the comparator circuit 20. The assigned bit number (n) is decided based on the relation between the dynamic range DR' and the threshold levels T1-T4. A quantization circuit 18 uses the dynamic range DR' and the assigned bit number n' to convert the data PDI after elimination of a minimum value into a code signal DT by the quantization for edge matching. Thus, the mismatching of different bit assignment number (n) different between the encoder side and the decoder side is prevented. |
| 申请公布号 |
JPH0353781(A) |
申请公布日期 |
1991.03.07 |
| 申请号 |
JP19890189889 |
申请日期 |
1989.07.21 |
| 申请人 |
SONY CORP |
发明人 |
KONDO TETSUJIRO;YADA ATSUO |
| 分类号 |
H04N19/115;H04N1/41;H04N7/24;H04N19/00;H04N19/126;H04N19/136;H04N19/172;H04N19/196;H04N19/423;H04N19/46;H04N19/70;H04N19/85;H04N19/86;H04N19/98 |
主分类号 |
H04N19/115 |
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