发明名称 |
COMPENSATED PHASE LOCKED LOOP CIRCUIT |
摘要 |
A Phase Locked Loop (PLL) circuit (100) includes a compensation circuit (120) which corrects for non-linear sensitivity of a varactor of a voltage controlled oscillator (VCO) (104) which is part of the circuit. The varactor is employed as a capacitance tuning element. The compensation circuit controls the sensitivity of a charging/discharging circuit (a charge pump 114) of the PLL circuit with a feedback signal which is derived from an input to the VCO. The sensitivity characteristic of the charge pump is made the complement of the non-linear portion of the VCO sensitivity characteristic. |
申请公布号 |
AU6139590(A) |
申请公布日期 |
1991.03.07 |
申请号 |
AU19900061395 |
申请日期 |
1990.08.28 |
申请人 |
DELCO ELECTRONICS CORPORATION |
发明人 |
RICHARD ALBERT KENNEDY;SEYED RAMEZAN ZARABADI |
分类号 |
H03L7/18;H03J5/02;H03L7/089;H03L7/093 |
主分类号 |
H03L7/18 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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