| 摘要 |
PURPOSE:To make a check by providing plural various error holding circuits and an error writing circuit which implants an error by a bus connecting the error holding circuits in series. CONSTITUTION:The error holding circuits 10, 20, 30 - n0 are so constituted that shift paths 101, 201, 301 - n01 are selected as input with an error write/read signal 211 and the values are inputted with trailing edges of clock signals 214. When (n) clock signals 214 are inputted in this state, an optional value from an implanted data signal 217 can be set in the error holding circuits 10, 20, 30 - n0. Error reading operation is carried out in this state to check whether error information is equal to the written value or not. Consequently, the normalcy of error reading operation and the error holding circuits 10, 20, 30 - n0 can be checked. |
