| 摘要 |
<p>PURPOSE:To eliminate the need to execute a flag reset instruction and to simplify hardware and to lighten the load on software by providing a delay circuit which consists of an RS flip-flop and holds its input state for a next instruction cycle. CONSTITUTION:The microcomputer is equipped with an instruction decoder 1 which decodes a mode setting instruction, the RS flip-flop 2 which delays the output of the decoder 1 to specific timing of a next instruction cycle, and a data switching circuit 3 which selects and outputs the data of a RAM 6 or register 7 and the data of an accumulator 4 to the input terminal of an ALU 5 on the side of the accumulator 4 according to the output of the flip-flop 2. Then a memory mode is reset automatically at the end of the instruction cycle right after the setting of the memory mode. Consequently, the flag reset instruction need not be executed, the constitution of the instruction decoder is simplified, and the load on the software can be lightened.</p> |
