| 摘要 |
PURPOSE:To generate a system clock synchronously with an input clock with a digital circuit by providing a counter counting a prescribed number of high speed clocks of a prescribed frequency by a prescribed count so as to stop the operation, a counter generating the system clock through the frequency division of the output and a digital differentiating circuit. CONSTITUTION:When a 1st counter 61 consists of, e.g. 8-bit and its enable terminal EN is brought into a stop level with a carry output CO when high speed clocks are counted by 26 after clearing. Since the period of an input clock is longer than 256 periods of high speed clocks, the counter 61 stops the operation till it is cleared by an output of a digital differentiating circuit 63. A 2nd counter 62 frequency-divides the output of the counter 61 to generate various system clocks. The digital differentiating circuit 63 generates a differentiating pulse corresponding to the rise or fall of the input clock to clear the counters 61, 62 simultaneously. Thus, the system clock synchronously with the input lock is generated by a digital circuit only. |
