| 摘要 |
PURPOSE:To eliminate decrease in fraction defective relief by composing the gate electrode of a MOS type transistor of a laminated layer structure of a polycrystalline silicon layer and a high melting point metal silicide layer, and composing a fuse element only of a polycrystalline silicon layer. CONSTITUTION:A polycrystalline silicon layer 15 is deposited and a high melting point metal silicide is deposited on the layer 15 as a wiring material of a gate electrode and a redundancy circuit fuse for forming a MOSFET on a semiconductor substrate 11. Thereafter, interlayer insulating films 20, 21 are deposited, the wirings are patterned, only the fuse is then opened, only a high melting point metal silicide layer 16 is selectively etched to expose the layer 15 on an uppermost layer, and a fuse wiring layer made only of the layer 15 is formed. Thus, an easily melting fuse can be formed while the gate electrode of the MOSFET remains reduced in its resistance, thereby improving the fraction relief of an improper cell. |
