| 摘要 |
<p>The present disclosure describes a clock circuit, together with a control current generator (11) and a ratio circuit (12) coupled thereto. The ratio circuit, of the invention, utilizes at least two capacitors (C1, C2) each of which is coupled in series with a respective transistor and arranged in parallel with one another. Each capacitor transistor pair is in parallel to the other and coupled between the control current generator and ground so that at least one of the transistors in a selected capacitor transistor series can be selectively turned off while the other can be directly controlled by the clock cycle. The present invention is thus a circuit, for generating timing edges within a clock cycle which timing edges can be any fraction of the clock cycle, which comprises a clock, a controlled current generator, and a ratio circuit coupled to the clock and the generator. The preferred embodiment of this invention comprises at least two capacitor-transistor pairs coupled in parallel between the generator and ground with the clock being coupled to the control electrode of one of the transistors and being coupled to the control electrode of the other transistor together with a turn-off signal source. Means (Q3, Q4) for discharging the capacitors are included in the circuit.</p> |
