发明名称 POWER-ON RESET MONITOR CIRCUIT
摘要 <p>PURPOSE:To prevent the malfunctions due to the variance of the rise-up time of a power supply by using the 1st and 2nd diodes, a pnp type transistor TR, and an npn type TR. CONSTITUTION:When the power voltage Vcc1 rises up and reaches a prescribed level in a power-on reset circuit 1, a reset signal V1 rises up after a fixed time. A reset signal V2 performs the same action in accordance with the power voltage Vcc2. When both reset signals V1 and V2 are set at H levels, no current flows to both diodes D1 and D2. Thus a pnp type TR Q1 and an npn type TR Q2 are not turned on and therefore an output signal V3 is set at an H level. As a result, both circuits 1 can output continuously the signals showing the reset states until they output the reset signals to release the reset states even though an error produced between both rise-up times of the power voltage when the power is supplied to both circuits 1.</p>
申请公布号 JPH0351903(A) 申请公布日期 1991.03.06
申请号 JP19890187699 申请日期 1989.07.19
申请人 NEC IBARAKI LTD 发明人 YOKOSE SUSUMU
分类号 G06F1/24 主分类号 G06F1/24
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