| 摘要 |
An integrated circuit arrangement comprises a circuit (2) with first resistances (r2, r3, r4) in series with a plurality of input connections (P2, P3, P4), a tristate logic (TR2, TR3, TR4) associated with each connection and further resistances (R2, R3, R4) between each connection and each logic device, means (D) causing each logic device to be operated between a normally high impedance state and two different potential states and a comparator (C) monitoring the potential of each of the connections (P2, P3, P4) corresponding to each of the different potential states and affording a fault indication if a fault exists in the circuit (2). <IMAGE> |
