| 发明名称 |
Microprocessor having predecoder unit and main decoder unit operating in pipeline processing manner. |
| 摘要 |
<p>Microprocessor (100) having an instruction decoding operation that is performed by a predecoder unit (130) and a main decoder unit (150) which operates in a pipeline manner by providing between those two units a buffer (140) for temporarily storing information from the predecoder unit (130).</p> |
| 申请公布号 |
EP0415366(A2) |
申请公布日期 |
1991.03.06 |
| 申请号 |
EP19900116506 |
申请日期 |
1990.08.28 |
| 申请人 |
NEC CORPORATION |
发明人 |
SUZUKI, NARIKO, C/O NEC CORPORATION |
| 分类号 |
G06F9/30;G06F9/38 |
主分类号 |
G06F9/30 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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