发明名称 CLOCK GENERATING CIRCUIT
摘要 <p>PURPOSE:To improve the picture quality independently of the input of a standard signal or a nonstandard signal by applying phase-lock of a line lock clock to a burst lock clock only when an input video signal is the standard signal. CONSTITUTION:A standard/nonstandard signal detection circuit 106 detects whether a video signal from a terminal 101 is a standard signal satisfying the prescribed standard or a nonstandard signal not meeting the standard. When the video signal is detected to be the standard signal, a switch 108b is controlled with a signal delayed by a delay circuit 113. A switch 108b phase-locks a line lock clock 103 to a burst lock clock 105. When the nonstandard signal is inputted to a line lock clock generating circuit 102, the clock 103 is given and when the standard signal is inputted, the clock 105 or the clock 103 synchronously with the clock 105 is given. Thus, even when any signal is inputted, the picture quality is improved.</p>
申请公布号 JPH0350979(A) 申请公布日期 1991.03.05
申请号 JP19890184686 申请日期 1989.07.19
申请人 HITACHI LTD;HITACHI VIDEO ENG CO LTD 发明人 KURITA TOSHIYUKI;SEKIYA HIROSHI;NAKAGAKI NOBUFUMI
分类号 H04N5/06;H04N3/16;H04N9/44;H04N19/00;H04N19/423;H04N19/85 主分类号 H04N5/06
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