| 摘要 |
MULTIPLE FREQUENCY DIGITAL PLL An improved multiple frequency digital phase-locked loop circuit is described. The improved digital phaselocked loops utilizes a single circuit to effect both phase and frequency adjustments. The multiple frequency digital phase-locked loop effects phase adjustments by selectively combining or subtracting a reference clock signal with a derived programmable clock signal thereby generating a composite digital phase-locked loop clock signal. The multiple frequency provides frequency adjustments by selectively adding or subtracting pulses from the composite clock signal at a rate determined by a programmably controllable clock signal. The improved multifrequency digital phase-locked loop is suitable for use as a tone detector with the addition of a lock detector wherein the phase-locked loop can be programmed for a plurality of known operating frequencies. |
