| 摘要 |
An asynchronous arbiter circuit processes multiple different address signals that request access to the same memory location during the same memroy cycle. The circuit employs two sets of latches. The circuit recognizes access request signals and refresh request signals. For each type of request signal recognized, an associated first latch stores the value of the request signal received, and outputs a first latch output signal. An associated second latch receives the first output latch signal and translates that into a logic state that is long enough to ascertain whether additional request signals have been inputted into the circuit during the memory cycle. A delay element delays one of the request signals received prior to the signals being inputted into the cycle request logic element. The time period of the delay is determined based upon priority accorded to the particular signals.
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