发明名称 SERIAL DATA RECEIVING CIRCUIT IN EQUIPMENT
摘要 PURPOSE:To automatically select data with a safe phase and to eliminate dispersion in the delay of a clock distribution system and a data transmission system by detecting the noncoincidence of each data whose re-timing is taken with clocks delayed with different phases. CONSTITUTION:The data in which the re-timing of received data is taken with the positive phase of the clock, and the data in which the re-timing of the received data is taken with the negative phase of the clock and furthermore, the re-timing is taken with the positive phase of the clock are inputted to a selection circuit SEL. Also, the data in which the re-timing of the received data is taken with the clock whose phase is delayed by 1/4-phase than the clock of positive phase and the re-timing is taken with the clock whose phase is further delayed by 3/4-phase is compared EOR with the data in which the re-timing of the reception data is taken with the clock delayed by 3/4-phase. Noncoincidence information that is a comparison result is latched, and is set as the control signal of the circuit SEL, and the re-timing phase of the received data can be selected.
申请公布号 JPH0348545(A) 申请公布日期 1991.03.01
申请号 JP19890183893 申请日期 1989.07.17
申请人 NEC CORP 发明人 YAMADA KIYOHISA
分类号 H04L25/40;H04L7/02 主分类号 H04L25/40
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