| 摘要 |
PURPOSE:To shorten a processing time for detection of a key operation without awaiting the completion of a discharge in an input signal line by performing a fast discharging of a charge on the input signal line at a timing before the application of a voltage pulse to an output signal line. CONSTITUTION:For example, only when a key switch 1 alone is turned ON, a CPU 7' makes a discharge voltage DIS high during a high period at all of output terminals KO1-3. During the period, an FET8 is turned ON and a charge stored in a capacitance 6 is discharged fast. Therefore, the CPU 7' can load input voltage immediately after the terminals KO1-KO3 go to low so that time per cycle can be shortened for the detection of a key operation. A resistance value of a resistor 5 becomes a large value while the terminals KO-KO3 are low. This can minimize the number of signal lines as a whole thereby achieving a higher processing efficiency and a reduction in the size of circuits with a less number of pins as densified in an LSI. |
