发明名称 HIDDEN-LINE ERASING PROCESSOR
摘要 PURPOSE:To speedily output a hidden-line erased result by adopting algorithm conscious of relation between blocks or relation between a line under calculation and the block and saving data, which are converted for hidden-line erasure, on a shared memory. CONSTITUTION:A data converting means 1-1 fetches three-dimensional data, to which the hidden line erasure is executed, and the data are put in order and converted for each block. Then, the converted data are accumulated in a shared memory 1-2. A data set part 1-3 sets the data to the memory 1-2 according to prescribed specification. A hidden line erasure calculating means 1-4 adopts the algorithm conscious of the relation between the blocks or the relation between the line under the calculation and the block by using the data on the memory 1-2. The hidden line erasing calculation is executed and the calculated result is successively displayed as two-dimensional data on the screen of a displaying and registering part 1-5. The data converted for the hidden line erasion are saved on the shared memory 1-2 and time is prevented from being wasted. Then, the result of the hidden line erasure is speedily outputted.
申请公布号 JPH0348983(A) 申请公布日期 1991.03.01
申请号 JP19890185444 申请日期 1989.07.17
申请人 NEC CORP 发明人 SONOBE KAZUKO
分类号 G06T15/40 主分类号 G06T15/40
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