| 摘要 |
PURPOSE:To accelerate the operation of a memory and to perform a large scale integration by selectively forming an insulating region for restricting the shape of an emitter region deeper than a buried layer in an emitter region of a lateral bipolar transistor. CONSTITUTION:A transistor load type memory cell is composed of a vertical bipolar transistor Q1 formed in a semiconductor layer and a lateral bipolar transistor Q2 having a base region 6 of the transistor Q1 as a collector region, and insulating regions 4A, 4B for restricting the shape of an emitter region 5 are selectively formed deeper than a buried layer 2 provided at the lower side of the semiconductor layer in the region 5 of the transistor Q2. In this case, the region 5 effective by the regions 4A, 4B can be increased in length, and current amplification factor of the transistor Q3 can be reduced. Thus, a high speed and a high integration can be realized. |
