| 摘要 |
PURPOSE:To eliminate both positive and negative glitches in a minimum delay time by storing information short-circuiting a delay means in a memory means in advance and setting a proper glitch eliminating circuit in response to the generated glitch. CONSTITUTION:An input signal including glitch is inputted to one terminal of a NAND gate 22 and a NOR gate 23 directly on one hand and inputted to a delay circuit 21 on the other hand. A prescribed delay stage 21A of the delay circuit 21 is short-circuited according to the information stored in advance in a semiconductor memory array 26 with a control signal from a semiconductor switch array 25. As a result, the input signal given directly and the input signal through the delay circuit 21 give a discrete phase difference in response to the delay stage numbers to be short-circuited to decide the maximum width of the glitch able to be eliminated by a glitch elimination circuit 20. Then a NAND gate 22 eliminates the glitch superimposed on a low level and a NOR gate 23 and an inverter 24 placed succeeding to the gate eliminate the glitch superimposed on a high level. Thus, both positive and negative glitches are eliminated in a minimum delay time. |
