| 摘要 |
PURPOSE:To introduce an always accurate video detection output in following to only a video intermediate frequency signal in a timing with a shallow modulation by switching the state of a PLL and a holding circuit in response to a lock detection signal, a signal intensity detection signal and a modulation detection signal. CONSTITUTION:The above circuit consists of a phase locked loop(PLL) comprising a phase detection circuit 8', a low pass filter 9', and a voltage controlled oscillator 6, a synchronizing detection circuit 4, a PLL lock detection means 10 or the like, and the PLL circuits 6, 8', 9' switch the PLL state and the hold state in response to a lock detection signal, a signal intensity detection signal and a modulation detection signal. Thus, when the hold state is set in the timing with a deep modulation in the video intermediate frequency signal, the PLL output does not follow the video intermediate frequency signal in the timing with the deep modulation but follows only the video intermediate frequency signal in the timing with a shallow modulation and an accurate video detection output is always obtained. |
