| 摘要 |
<p>PURPOSE:To allow the device to cope with various clock frequencies by varying a delay with a decode signal sequentially and varying a decode signal sequentially till the timing between outputs of a 1st and a 2nd delay circuit retarding the clock signal and the data inputted externally is discriminated to be proper. CONSTITUTION:Upon the receipt of a clock signal, a pattern generating circuit 13 generates a synchronization pattern as a data and the synchronization pattern is given to one selection input of a multiplexer 14. On the other hand, an output of a counter 21 receiving a data is outputted to a decoder 22, the decoder 22 decodes the counter output to output a selection signal to multiplexers 23, 24. The multiplexer 23 uses the selection signal to select one of data with 3 kinds of different delays from an IC 11 and the multiplexer 24 selects and outputs one of clock signals with 3 kinds of different delays. Thus, a change in various clock frequencies and clock duty cycles is absorbed.</p> |
