PACKET SWITCHING SYSTEM HAVING BUS MATRIX SWITCH

摘要

A packet switching system having a matrix switch including input packet transfer buses (61 - 6n) and output packet transfer buses (81 - 8n). Transfer buffers or gates are provided at cross points of the input and output packet transfer buses. An input packet is supplied to the matrix switch through a transfer control circuit, and an output packet from the matrix switch is output through the transfer control circuit. The input packet is permitted to be applied to the matrix switch so that each of the output packet transfer buses has only one packet during one packet transfer cycle.