| 摘要 |
<p>PURPOSE:To easily transfer data between two CPUs by optionally access a memory from the two CPUs. CONSTITUTION:The CPUs 1, 2 of RP65C02 and ROMs 3, 4 of 256K bits and a static random access memory (SRAN) 5 are connected as main units. The CPUs 1, 2 for setting up addresses, data and control signals (R/the inverse of W) during the high period of an outputted clock are used and the two CPUs 1, 2 are driven by clocks whose phases are mutually reversed and the memory is accessed by either one of the CPUs. Consequently, one memory can be option ally accessed by the two CPUs 1, 2 and a large volume of data can be rapidly transferred between the CPUs through the memory.</p> |
