| 摘要 |
PURPOSE:To acquire an n-fold output frequency of a video frame frequency Fv and to reduce output jitter only by passing through two PLL circuits by switching the frequency dividing ration of a second frequency divider corresponding to a sampling frequency. CONSTITUTION:The frequency dividing ratio of a second frequency divider 5 is switched corresponding to the sampling frequency so as to select one frequency to satisfy a condition that an output frequency B of a frequency dividing block 3 is 30.K times to an n FV fold output frequency C composed by a PLL circuit 6 and 1/2<j> to the greatest common measure between the output frequency C and a 2<m>.fs fold frequency to an output A of a voltage control oscillator. Accordingly, the n-fold output frequency of the video frame frequency Fv synchronous to a PCM audio can be acquired only passing through two PLL circuits 2 and 6. Thus, the output jitter can be reduced to the video frame frequency Fv. |
