发明名称 DETECTING CIRCUIT FOR TIME LIMIT FAULT OF TIMER
摘要 PURPOSE:To secure locking during the occurrence of a fault by faciliating the cooperation of a time when a lock output is sent out by comparing variation states of charging voltages, and thus detecting a time limit fault before the output of a timer to be monitored is sent out. CONSTITUTION:In parallel to the timer circuit 4 of a timer 3 to be monitored, a timer circuit 14 for comparison wherein a resistance R2 having the same value with the resistance R1 of the timer and a capacitor C2 having the same value with a capacitor C1 and connected in series is provided. A timer fault judging circuit 16 is connected to a differential voltage detecting circuit 18 with an operational amplifier 17. To the inverted input terminal of the operational amplifier 17 where a feedback resistance R13 is connected, a charging voltage v1 led out of the capacitor C1 is applied through an input terminal R11, and to the uninverted input terminal of the amplifier 17, a charging voltage v2 led out of the capacitor C2 is applied through an input resistance R12. The univerted input terminal of the amplifier 17 is led out as the output terminal of the circuit 18 through a resistance R14, and a voltage v0 between it and the output terminal of the amplifier 17 is inputted as a difference output to a level detector 19.
申请公布号 JPS57170627(A) 申请公布日期 1982.10.20
申请号 JP19810054647 申请日期 1981.04.10
申请人 MITSUBISHI DENKI KK 发明人 EDA NOBUO
分类号 H03K5/04;H03K17/28 主分类号 H03K5/04
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