| 摘要 |
PURPOSE:To cause no hindrance to a user system by adding a clock signal gate circuit to a peripheral evaluation chip. CONSTITUTION:A clock signal gate 25 contains a 2-input AND gate 33 which outputs an AND signal SAND obtained between an inverted supervisor mode signal SSM and a clock signal SCK. Then the gate 25 is put between a clock signal line 7 of a peripheral evaluation chip 2 and the CK terminal of a counter unit 10. The signal SSM is equal to '1' in a supervisory mode, therefore the supply of the clock signal SCK is inhibited to the unit 10. Thus the unit 10 stops its counting action. On the other hand, the signals SCK are continuously supplied to the clock terminal CK of a PWM unit 11. As a result, a motor, etc., are never broken and the display is never confused even though a debugging operation using a user system is directly carried out. |
