| 摘要 |
A synchronous delay line with quadrature clock phases provides for an improved output from the taps of a delay line. The delay line is comprised of a phase generator, a plurality of voltage controlled delay stages arranged serially, wherein the last VCD stage is coupled to a sample-and-hold circuit for providing an analog control voltage for controlling the delay. The phase generator generates in-phase clock signals to the interior delay stages, but provides quadrature clock phases to the delay stages at the extremities of the delay line. The quadrature clock phases provide for the low and high times of the tap outputs near the extremities of the synchronous delay line to be sufficiently long in duration for use in MOS circuits.
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