| 摘要 |
A DSB-SC signal is demodulated using an up/down counter, the count direction of which is alternately switched in synchronism with the polarity of a reference carrier signal for the DSB-SC signal. The converter includes an integrator, a comparator and a charge-rebalancing current source to reset the integrator. Correction of the court value of the up/down counter is obtained by tracking and storing a partial-bit analog signal. The partial-bit analog signal corresponds to and is obtained from the output of the integrator just prior to the pahse transition of the reference carrier signal. A capacitor samples the partial-bit analog signal information and subsequently transfers that information to the integrator input. The transfer of a charge of twice the magnitude and opposite polarity to the integrator compensates for the partial bit analog signal as it is detected by the up/down counter. A digital system for converting the partial-bit analog signal to a binary code word is provided. A number of these binary code words are summed and when the resultant sum exceeds a certain value a correction count for the up/down counter is provided to increment the up/down counter.
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