| 摘要 |
<p>PURPOSE:To improve reliability by providing a means to prohibit a monitor timer only in a first instruction or several instructions, and a means to provide an instruction for always making the timer effective. CONSTITUTION:A signal WDPRHHBT to prohibit the monitor timer is a signal to be '1' at the time of the prohibiting instruction. While the signal is '1', the signal is inverted and inputted through a NAND a8 to a NOR a7. When a 3-bit down counter 4 overflows and '1' is outputted to a COUNTOUT signal, the WDPRHBT is not outputted by the NAND a8. The contents of a latch 4 are also made '0' and a SYNC signal is not outputted by an AND a10. Thus, when the instruction to prohibit the monitor timer is not executed in the first 8 instructions, the 7th bit of a monitor timer control register 2 can not be made '1' and the monitor timer can not be prohibited. Reversely, there is no limit in the instruction to make the timer effective and the 7th bit of the register 2 can be made always '0'.</p> |
