| 摘要 |
PURPOSE:To execute a high speed operation by delaying input data by an (n) bit period, erasing the data before (n) bits and executing an error check, and taking the synchronization of an input signal by an output of a result of error check. CONSTITUTION:Input data is delayed by an (n) bit period corresponding to an insertion period of error check data in a delaying means 1. Subsequently, from the input data and an output of the delaying means 1, data before (n) bits in the input data are erased and an error check is executed in an error checking means 2. In an output of a result of this error check, the influence of the data before the insertion period of the error check data is eliminated. Accordingly, since the error check data can be outputted in accordance with the insertion period of the error check data, the synchronization of an input signal can be taken by the output of the result of error check. In such a way, a delay time of a gate becomes small, and a high speed operation can be executed. |
