发明名称 LATCH-UP PREVENTION CIRCUIT FOR CMOS CIRCUIT
摘要 PURPOSE:To prevent the latch-up of a CMOS circuit requiring multipower supplies, by providing the CMOS circuit enabling indirect plug-in without using a special connector. CONSTITUTION:The base of an NPN transistor (TR) 38 is connected to a ground terminal 21, and the emitter is connected to a negative power supply terminal 23 via a resistor 39. A TR37 the base of which is connected to the collection of the TR38, the emitter of which is connected to a positive power supply terminal 22, and the collector of which is connected to a positive power supply input terminal of a CMOS circuit 33, and an operational amplifier 36 for voltage supply use, the non-inverting input terminal is connected to the collector of the TR37 and the output terminal is connected to the input terminal of other voltage of the circuit 33 are provided. The negative power supply input terminal of the circuit 33 is connected to the terminal 23 and the order of application of power supply of the circuit 33 requiring multi-power-supply is in the order of the negative power supply, the positive power supply and a reference power supply.
申请公布号 JPS57174935(A) 申请公布日期 1982.10.27
申请号 JP19810059174 申请日期 1981.04.21
申请人 NIPPON DENKI KK 发明人 YANO KAORU;HAYASHI KENJI
分类号 H03K19/0948;H03K17/08;H03K17/687 主分类号 H03K19/0948
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