发明名称 |
High speed computer data transfer system |
摘要 |
A high speed computer data transfer system includes a clamping circuit for limiting pre-charge voltages in the case where multiple pre-charge cycles occur before a pull-down operation. Data bus voltage swings between logic high and logic low levels as well as pull-down times are reduced, thus lowering the time needed to transfer the data. The preferred embodiment is implemented using complementary metal-oxide-semiconductor (CMOS) technology.
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申请公布号 |
US4992678(A) |
申请公布日期 |
1991.02.12 |
申请号 |
US19880284644 |
申请日期 |
1988.12.15 |
申请人 |
NCR CORPORATION |
发明人 |
SANWO, IKUO J.;MILBY, GREGORY H.;KIM, MOO Y. |
分类号 |
G06F13/40;H03K19/017 |
主分类号 |
G06F13/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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