Logic level converting circuit

摘要

A logic level converting circuit for converting an ECL level signal to a CMOS level signal comprises complementary signal generating means and level shifting means. The complementary signal generating means generates complementary signals in response to the ECL level input signal and a first reference voltage. The level shifting means operates as a flip-flop circuit, and includes a first and a second PMOS transistors which are either conductive or not conductive in response to the relationship between the complementary signals and a second reference voltage applied to the gate electrodes of the PMOS transistors.