| 摘要 |
PURPOSE:To easily obtain a quantizer as a processor incorporating a multiplier in which a step interval is increased as a signal level larger by adopting cascade connection of quantizing means. CONSTITUTION:A quantizer is divided into n-stages, and a discrimination circuit 1 of the 1st stage discriminates whether a level of an input signal is a threshold level T1 or over, a threshold level -T1 or below, or a level inbetween and applies a prescribed calculation. A discrimination circuit 7 of the 2nd stage discriminates whether a level of an input signal is a threshold level of l2+1 or over, a threshold level -(l2+1) or below, or a level inbetween and applies a prescribed calculation, and the circuit in the 3rd-n-th stages acts similarly to that of the 2nd stage. As a result, quantization is applied at a step difference g1 from the input level T1 till T1+l2.g1 and quantization is applied at a step difference k2.g1 from the input level T1+ld2.g1 till T1+l2.g1+(l3-l2).k2.g1. Thus, the quantizer increasing the step difference with a larger level is attained easily by means of a processor incorporating a multiplier. |
