| 摘要 |
PURPOSE:To attain high speed operation by inputting a 1st signal to the base of a 1st transistor(TR), inputting a 2nd signal to each base of 3rd, 5th TRs and inputting a 3rd signal to the base of a 10-th TR respectively, applying a signal at a 2nd terminal to a data input terminal, and applying a signal of a data output terminal to a 8th TR. CONSTITUTION:An initial setting signal (1st signal) is inputted to the base of a 1st TR T1, an inverted limit signal (2nd signal) S2 is inputted to both bases of 3rd, 5th TRs T3, T5 and an initial set control signal (3rd signal) S3 is inputted to the base of a 10th TR T10, respectively. Moreover, a 1st reference voltage V1 is fed to each base of the 2nd, 4th, 6th TRs T2, T4, T6 and a 2nd reference voltage V2 is fed to the base of a 9th TR T9 and a 3rd reference voltage V3 is fed to the base of a 7th TR T7. Furthermore, a signal at a 2nd terminal N2 is fed to a data input terminal I and a signal at a data output terminal Q is fed to the 8th TR 8. Thus, the operating speed is quickened. |
